VHDL: 4 bit Ripple Carry Adder with Testbench (Gate Level Modelling)

    I want to share the VHDL code for a 4-bit Ripple carry adder(RCA) implemented using basic logic gates such as AND, OR, XOR etc.. The entity port has two 4-bit inputs and one 1-bit carry input. There are two outputs, a 4-bit sum and a 1-bit carry.

    Why is this adder called ripple carry? If you look at the block diagram below, the respective bits from the input operands are fed to the full adders. And then the carry out from each full adder is fed as the carry in of the next full adder. In a way you can say that the carry is rippled from the right(least significant bit position) to the left(most significant bit position) side. 

VHDL Code for 4 bit Ripple Carry Adder:

--libraries to be used are specified here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--entity declaration with port definitions
entity rc_adder is --ripple carry adder
port(num1 : in unsigned(3 downto 0);  --4 bit input 1
    num2 : in unsigned(3 downto 0);   --4 bit input 2
    sum : out unsigned(3 downto 0);   --4 bit sum
    carry : out std_logic                     -- carry out.
);
end rc_adder;

--architecture of entity
architecture gate_level of rc_adder is

--temporary signal declarations(for intermediate carry's).
signal c0,c1,c2,c3 : std_logic := '0';

begin  

--first full adder
sum(0) <= num1(0) xor num2(0);  --sum calculation
c0 <= num1(0) and num2(0);      --carry calculation
--second full adder
sum(1) <= num1(1) xor num2(1) xor c0;
c1 <= (num1(1) and num2(1)) or (num1(1) and c0) or (num2(1) and c0);
--third full adder
sum(2) <= num1(2) xor num2(2) xor c1;
c2 <= (num1(2) and num2(2)) or (num1(2) and c1) or (num2(2) and c1);
--fourth(final) full adder
sum(3) <= num1(3) xor num2(3) xor c2;
c3 <= (num1(3) and num2(3)) or (num1(3) and c2) or (num2(3) and c2);
--final carry assignment
carry <= c3;

end gate_level;

A little tip on Concurrency in VHDL:

    We have used basic logic gates here to implement the adder. This is known as Gate Level Modelling in VHDL. 

    

    All the statements in the architecture body in the above code are concurrent, which means they execute parallelly. But since the output of one gate is connected as the input to another, they appear as concatenated and looks as if the first line executes first before the second line. 

    If you are not convinced of what I am saying, you can change the line order as you like, and you would still get the same simulation waveform.

Testbench code for Ripple carry adder:

--library declarations
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--this is how entity for your testbench code has to be declared.
entity testbench is
end testbench;

architecture behavior of testbench is

--signal declarations.
signal num1,num2,sum : unsigned(3 downto 0) :=(others => '0');
signal carry :  std_logic:='0';

begin

--entity instantiation
adder : entity work.rc_adder 
    port map(num1 => num1,
        num2 => num2,
        sum => sum,
        carry => carry);

--definition of simulation process
stimulus : process
begin
    --result should be sum=11 and carry=0
    num1 <= to_unsigned(2,4);  
    num2 <= to_unsigned(9,4);  
    wait for 2 ns; 

    --result should be sum=13 and carry=0
    num1 <= to_unsigned(10,4);  
    num2 <= to_unsigned(3,4);  
    wait for 2 ns;

    --result should be sum=14 and carry=0
    num1 <= to_unsigned(8,4);  
    num2 <= to_unsigned(6,4);  
    wait for 2 ns;

    --result should be sum=0 and carry=1
    num1 <= to_unsigned(10,4);  
    num2 <= to_unsigned(6,4);  
    --more input combinations can be given here.
    wait;
end process stimulus;

end;

Simulation Waveform:

The codes were simulated in Modelsim. This is a screenshot of the waveform.

RTL Schematic:

The code was synthesized using Xilinx ISE . The RTL schematic of the design is shown below:

Note :- Use RTL Viewer to get a closer look on how your design is actually implemented in hardware.