VHDL: 4 to 1 Multiplexer(MUX) Using Case statements with Testbench

   I want to share the VHDL code for a 4 : 1 MUX (multiplexer) implemented using case statements. The entity port has four 1-bit inputs and one 2-bit select input. The output is a 1-bit wire.

VHDL Code for 4:1 MUX:

--library declarations.
library ieee;
use ieee.std_logic_1164.all;

entity multiplexer4_1 is
port(i0 : in std_logic; --input wire 1
    i1 : in std_logic; --input wire 2
    i2 : in std_logic; --input wire 3
    i3 : in std_logic; --input wire 4
    sel : in std_logic_vector(1 downto 0);  --select input
    bitout : out std_logic  --output
    );
end multiplexer4_1;

architecture Behavioral of multiplexer4_1 is

begin

--make sure to include all signals in the process sensitivity list which affects the output.
--The below process contains the behavioral description of 4:1 MUX.
process(i0,i1,i2,i3,sel) 
begin
case sel is
    when "00" => bitout <= i0;
    when "01" => bitout <= i1;
    when "10" => bitout <= i2;
    when others => bitout <= i3;
end case;
end process;

end Behavioral;

The process above is a combinatorial process. Every time any of the signals in the process sensitivity list is changed, the process is 'invoked' and the logic inside is as if 'executed'. This explanation is just for beginners to get an inkling on what is going on. But don't take it too seriously, as you will need to refine this understanding as you get to know more of how VHDL works.

Testbench code for 4:1 MUX:

--library declarations
library ieee;
use ieee.std_logic_1164.all;

--testbench entity is always empty. no ports to be declared here.
entity testbench is
end testbench;

architecture behavior of testbench is

--internal signals
signal i0,i1,i2,i3,bitout :  std_logic:='0';
signal sel :  std_logic_vector(1 downto 0):="00";

begin

--entity instantiation with named association style
mux_4_1 : entity work.multiplexer4_1 
    port map(i0 => i0,
        i1 => i1,
        i2 => i2,
        i3 => i3,
        sel => sel,
        bitout => bitout);

stimulus : process
begin
    --set the four input lines
    i0<='1';    i1<='0';    i2<='1';    i3<='0';
    --wait for 2 ns after changing 'select' input each time,
    --so that we can see the change in simulation waveform
    sel <="00"; 
    wait for 2 ns; 
    sel <="01";
    wait for 2 ns;
    sel <="10";
    wait for 2 ns;
    sel <="11";
    wait for 2 ns;
    --more input combinations can be given here.
    wait;
end process stimulus;

end;

Simulation Waveform:

The codes were simulated in Xilinx ISE. This is a screenshot of the waveform

RTL Schematic:

The code was successfully synthesized in Xilinx ISE. The RTL schematic of the design is shown below.

Note :- Use RTL Viewer to get a closer look on how your design is actually implemented in hardware.

Note2 :- You might have seen my blog article, why you should use signed/unsigned data types instead of std_logic_vector(SLV). But here the sel input is declared as std_logic_vector. You might be wondering, why?

This was a deliberate decision. The idea is not to completely abandon SLV, but use it only for signals of general purpose, where you don't need to perform any logical or arithmetical operations on them.