VHDL: Difference between rising_edge(clk) and (clk'event and clk='1')

    Generally you might have noticed that there are two ways in which we can detect the edge of a clock. 

1. rising_edge(clk) or falling_edge(clk).
2. clk'event and clk='1' or clk'event and clk='0'

    You might have been using either of these methods without really understanding if there is a difference between them. But there is a difference between them and this article intends to bring clarity on this.

Consider the following VHDL snippet:

clk_process : process
begin
    clk <= '0';
    wait for clk_period/2; --for 0.5 ns signal is '0'.
    clk <= '1';
    wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;

process(clk)
begin
    if(rising_edge(clk)) then
        xr <= not xr;
    end if;

    if(clk'event and clk='1') then
        x0 <= not x0;
    end if;
end process;

When the value of clk goes from '0' to '1', that is when it changes from low to high, I toggle the bits, xr and x0. If you run the above code, the simulation waveform will look like this:

Now you may ask where is the difference? There is no difference in this particular case. But let us slightly change the code snippet as follows:

clk_process : process
begin
    clk <= 'Z';          ----------Here is the change('Z' instead of '0').
    wait for clk_period/2; --for 0.5 ns signal is 'Z'.
    clk <= '1';
    wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;

process(clk)
begin
    if(rising_edge(clk)) then
        xr<= not xr;
    end if;

    if(clk'event and clk='1') then
        x0 <= not x0;
    end if;
end process;

The only difference in the new code is that instead of clk toggling between '0' and '1', we toggle it between 'Z' and '1'. Lets look at the simulation waveform:

Does this ring any bells? You can see that the signal xr doesn't change at all, while x0 changes just like it did in the first snippet. Why? To know why, lets look at the definition of rising_edge function as implemented in std_logic_1164 library:

FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
    RETURN (s'EVENT AND (To_X01(s) = '1') AND (To_X01(s'LAST_VALUE) = '0'));
END;

    As you can see the function returns TRUE only when the present value is '1' and the last value is '0'. If the past value is something like 'Z','U' etc. then it will return FALSE. This makes the code bug free, because the function returns only valid clock transitions, that means '0' to '1'. All the rules and examples shared above equally apply to falling_edge() function also.

The statement clk'event and clk='1' results in TRUE when the present value is '1' and there is an edge transition in the clk. It doesnt check whether the previous value is '0' or not.

Note :- Use rising_edge() or falling_edge() functions instead of clk'event statements in your VHDL projects.